1. Field of the Invention
This invention relates to data transfer control methods and controllers for universal serial bus (USB) interfaces that are used to interconnect host computers and peripheral devices together. Particularly, this invention relates to USB endpoint controllers that are installed in the peripheral devices to control communications with the host computers such as personal computers by the USB interfaces. The USB endpoint controllers are designed to provide high communications performance to the peripheral device such as hard-disk devices.
2. Description of the Related Art
Due to the worldwide popularization in use of the USB interfaces for personal computers and peripheral devices, there are strong tendencies in providing multiple functions for the peripheral devices having USB-compatible interfaces. Recently, manufacturers tend to provide the peripheral devices with complex functions. This gives rise to the necessities to increase the numbers of endpoints that correspond to destination of data transmission and reception in the viewpoints of the host computers such as the personal computers. Generally speaking, buffers configured by memories are allocated to the endpoints respectively. Therefore, the endpoints have buffering functions of data that are communicated between the host computers and peripheral devices.
The new standard of USB 2.0 whose specifications are updated in these days is expected as the future mainstream technology for the communications between the hosts and peripherals. It is determined that the standard USB 2.0 provides forty-times higher transfer speeds (i.e., 480 Mbps) as compared with the conventional ones. Accelerating the data transfer speeds noticeably increase maximal sizes of packets that are allowed by the standard USB 2.0. In the case of the bulk transfer that is suitable for transferring plenty of data, for example, the conventional standard USB 1.1 only allows the maximal packet size of sixty-four bytes, while the new standard USB 2.0 allows a broad range of packet sizes that range between one byte and 512 bytes. This means that the new standard allows maximally the eight-times larger size of packets as compared with the conventional one. As a result, the new standard inevitably increases the capacities of the buffers for use in the endpoints.
To realize the data transfer at a speed of 480 Megabits per second (or 480 Mbps), the new standard USB 2.0 requests the peripheral devices to have high performance in communications. To realize the high performance of communications in the peripheral devices, it is possible to propose the method for transferring plenty of data using double buffer configurations.
FIG. 15 shows a conventional example of a USB device controller 500 that actualizes the double buffer configuration. That is, the USB device controller 500 has a USB interface 501, a USB endpoint controller 502 and an external bus interface 503.
The USB interface 501 provides an interface for controlling a USB bus, by which data communications are performed with a host computer (not shown).
The external bus interface 503 provides an external bus interface for controlling a CPU or a DMA (i.e., Direct Memory Access) controller of a peripheral device (not shown).
The USB endpoint controller 502 configures an endpoint realizing a buffering function for data being communicated between the host computer and the USB interface 501. That is, the USB endpoint controller 502 has a transmission control block 504 and a reception control block 509 as well as a pair of transmission memories 521, 522 and a a pair of reception memories 523, 524. The transmission control block 504 accumulates data input by the external bus interface 530 in the transmission memories 521 and 522. In addition, it reads the accumulated data from the transmission memories 521, 522 to send them to the USB interface 501. In this case, the transmission control block 504 alternately switches over functions of the transmission memories 521 and 522. That is, one transmission memory is used to accumulate the input data from the external bus interface 503, while another transmission memory is used to output the accumulated data to the USB interface 501. Alternately switching over the functions of the transmission memories 521 and 522, it is possible to simultaneously perform the data accumulation and transfer with respect to the input data of the external bus interface 503. This brings an improvement in the communications performance of the peripheral device.
The reception control block 509 accumulates data input by the USB interface 501 in the reception memories 523 and 524. In addition, it reads the accumulated data from the reception memories 523 and 524 to send them to the external bus interface 503. As similar to the transmission control block 504 for alternately switching over functions of the transmission memories 521 and 522, the reception control block 509 alternately switches over functions of the reception memories 523 and 524. Hence, it is possible to simultaneously perform the data accumulation and transfer with respect to the input data of the USB interface 501.
Another example of the USB device controller is disclosed by Japanese Unexamined Patent Publication No. Hei 11-328069, which is characterized by using dual port memories for transmission and reception buffers.
With reference to FIG. 16, a USB device controller 600 using dual port memories is configured by a USB interface 601, a USB endpoint controller 602 and an external bus interface 603.
The USB endpoint controller 602 contains a transmission address setup control block 631 and a reception address setup control block 635 as well as a transmission dual port memory 638 and a reception dual port memory 639.
The transmission address setup control block 631 performs setup controls on addresses for the transmission dual port memory 638 with respect to each endpoint, while the reception address setup control block 635 performs setup controls on addresses for the reception dual port memory 639 with respect to each endpoint. Thus, it is possible to dynamically set the sizes and numbers of the transmission and reception buffers, so it is possible to efficiently use the memories in the USB endpoint controller 600.
A further example of the USB device controller is disclosed by Japanese Unexamined Patent Publication No. Hei 10-326251, which is characterized by dynamically allocating areas of the memory space to packets that are subjected to buffering.
With reference to FIG. 17, a USB device controller 700 for dynamically allocating areas of the memory space to packets is configured by a USB interface 701, a USB endpoint controller 702 and an external bus interface 703.
The USB endpoint controller 702 contains a DMA controller 740, an arbiter 742, a reception cue 743, a transmission cue 744, a memory manager 745, a map RAM 746 and a RAM 747.
The DMA controller 740 provides a cue control 741 therein. The RAM 747 functions as buffers for accumulating transmission and reception data. That is, packet data of the reception cue 743 and the transmission cue 744 are buffered in the RAM 747.
The arbiter 742 mediates accesses to the RAM 747 between the DMA controller 740 and the external bus interface 703. Thus, it enables asynchronous accesses to the RAM 747 from both sides.
The memory manager 745 and the map RAM 746 divide the overall area of the RAM 747 into plural areas. The cue control 741 controls the reception cue 743 and the transmission cue 744 so that their packet data are respectively accumulated in the divided areas of the RAM 747 respectively. Then, the accumulated data are read from the areas of the RAM 747 respectively.
The USB device controller 500 of FIG. 15 can improve the communications performance, however, it needs double sizes or capacities of memories for configuring the double buffers, which raises problems due to large circuit scales. If a chip of the aforementioned USB device controller is designed based on the new standard USB 2.0 that requires multiple functions and large capacities, it must increase the manufacturing cost so much.
The USB device controller 600 of FIG. 16 is designed such that address setup controls are made with intervention of the CPU, which inevitably causes intermittent suspension in transmission and reception of data during setup operations of addresses. This decreases the communications performance, so a load to the device driver should become increased. If the aforementioned USB device controller is designed based on the new standard USB 2.0 that further increases the data transfer speed, it is necessary to increase the processing speed of the USB endpoint controller, which is a bottleneck problem for the aforementioned USB device controller.
The USB device controller 700 of FIG. 17 needs memories for configuring the reception cue 743 and the transmission cue 744 respectively. In addition, it also needs special controls for the memory manager 745 and the arbiter 742. That is, the aforementioned USB device controller increases the scale of the peripheral circuitry of the memory. Further, the communications performance may be deteriorated if the data reception hold conditions continue because the reception buffer area is not secured in the memory area due to dynamic allocation of areas to packet data. Particularly, if the memory is occupied with transmission data due to the dynamic allocation, it is necessary to buffer the transmission data until arrival of an IN token from the host. Under the aforementioned condition, the UBS device controller cannot accept data, regardless of arrival of an OUT token from the host.
In addition, it is necessary to use packet identification numbers in handling the transmission data and reception data in the aforementioned USB device controller. That is, packet identification numbers are respectively allocated to the transmission data to be written to the memory, and then the reception data are read from the memory with reference to the packet identification numbers. Therefore, a load to the device driver becomes increased. Particularly, if the aforementioned USB device controller is designed based on the new standard USB 2.0 that further increases the data transfer speed, it is necessary to increase the processing speed of the USB endpoint controller, which is a bottleneck problem for the aforementioned USB device controller.
As described above, the conventional techniques have a difficulty of application to the new standard USB 2.0 because of the so-called xe2x80x98trade-offxe2x80x99 relationship being established between the circuit scale (or buffer capacity) and communications performance of the USB device controller. So, it is very difficult to meet the requirements of the new standard USB 2.0 by the conventional techniques.
It is an object of the invention to provide a data transfer method and a USB device controller that meets the requirements of the new standard USB 2.0 to demonstrate high communications performance while minimizing the circuit scale as small as possible.
A USB device controller of this invention is applied to a peripheral device that performs data communications with a host by using a transmission endpoint and a reception endpoint via a USB interface. Herein, a USB endpoint controller performs data transmission and data reception by using the reduced number of memories, which contribute to downsizing of the circuit scale of the USB device controller. The USB endpoint controller contains a transmission control block, a reception control block and a buffer switch control block as well as the memories. The buffer switch control block controls allocation of the memories to a transmission endpoint and a reception endpoint respectively in response to a type of a token issued from the host. In response to an OUT token, the data transmission is performed on the transmission endpoint that actualizes a double buffer configuration while the reception endpoint is also available in data reception by a single buffer configuration. In response to an IN token, the data reception is performed on the reception endpoint that actualizes a double buffer configuration while the transmission endpoint is also available in data transmission by a single buffer configuration. Because of the actualization of the double buffer configuration, it is possible to perform high-speed processing in communications of data, particularly transaction data based on the updated standard of USB 2.0.
For example, the USB endpoint controller contains three memories that are assigned as function-specified buffers and a common buffer respectively. Therefore, a first endpoint corresponding to one of the transmission endpoint and the reception endpoint actualizes a double buffer configuration using the function-specified buffer and the common buffer while a second endpoint corresponding to the other one actualizes a single buffer configuration using the function-specified buffer thereof. Herein, when a read buffer selected from among the function-specified buffer and the common buffer being allocated to the first endpoint becomes vacant, it is newly allocated to the second endpoint to allow actualization of the double buffer configuration.